1. Field of the Invention
The present invention relates to a cutting method suitable for cutting a QFN substrate, a wafer having TEG formed on predetermined division lines, or the like.
2. Description of the Related Art
In recent years, there has been a demand for more weight reductions and miniaturization in regard of such electrical apparatuses as cell phones and personal computers. As a device suited to the miniaturization, a technology called chip size package (CSP) has been developed and put to practical use in which a semiconductor chip is packaged to form a device. CSPs are formed, for example, by dividing a quad flat non-lead package (QFN) substrate into individual devices. A QFN substrate includes a plurality of semiconductor chips arranged at predetermined intervals, an electrode frame formed in a grid pattern so as to partition the semiconductor chips, electrode terminals arranged to extend like fishbone inward from the electrode frame and connected to a bonding pad formed on the surface of each semiconductor chip, and a resin layer molded so as to envelope each semiconductor chip and the electrode frame.
In order to divide the QFN substrate into the individual CSPs, the electrode frame of the QFN substrate is cut by a cutting apparatus having a rotatable cutting blade, and the fishbone-like electrode terminals are separated on the basis of each individual device, to form the CSPs (see, for example, Japanese Patent Laid-Open No. 2004-259936). On the other hand, a plurality of characteristic evaluation metal elements which are made of, for example, copper and are called test element group (TEG) are formed on the predetermined division lines (streets) of the semiconductor wafer, for evaluation of electrical characteristics of the semiconductor devices. With the plurality of characteristic evaluation metal elements formed on the predetermined division lines, the TEG can be cut and removed at the time of dicing the semiconductor wafer.
When a workpiece which includes metal (that is a ductile material) at a predetermined cutting position, such as a QFN substrate or a semiconductor wafer having TEG formed on predetermined division lines, is cut by a cutting blade, burrs would be generated at the metal parts. The burrs thus generated may cause short-circuit between terminals. Alternatively, during handling of the workpiece, dropping of burrs on the bonding pads or the like occurs, to cause bonding failure. In order to overcome such problems, a variety of methods have been proposed. Examples of the methods include a reciprocative cutting method for coping with the burr problem, as disclosed in Japanese Patent Laid-Open No. 2001-77055, and a method in which a burr-removing nozzle is provided to remove the burrs generated, as disclosed in Japanese Patent Laid-Open No. 2007-125667.